【发布时间】:2016-11-10 16:07:22
【问题描述】:
我正在按照文档 on Github 学习 Chisel
到目前为止,一切都完美无缺。但我被困在第 13 章,"Functional Module Creation"
我无法让代码工作。我在 chisel-template-project 的副本中创建了所有 .scala 类。以下是我为创建具有可变位宽的Mux4而编写/复制的内容:
/chisel-template/src/main/scala/Mux4.scala
import Chisel._
class Mux4(w: Int) extends Module {
val io = IO(new Bundle {
val sel = UInt(INPUT, 2)
val in0 = UInt(INPUT, w)
val in1 = UInt(INPUT, w)
val in2 = UInt(INPUT, w)
val in3 = UInt(INPUT, w)
val out = UInt(OUTPUT, w)
})
io.out := Mux2(io.sel(1),
Mux2(io.sel(0), io.in0, io.in1),
Mux2(io.sel(0), io.in2, io.in3))
}
class Mux2(w: Int) extends Module {
val io = IO(new Bundle {
val sel = Bool(INPUT)
val in0 = UInt(INPUT, w)
val in1 = UInt(INPUT, w)
val out = UInt(OUTPUT, w)
})
when(io.sel) {
io.out := io.in0
}.otherwise {
io.out := io.in1
}
}
object Mux2 {
def apply(sel: UInt, in0: UInt, in1: UInt): UInt = {
val m = new Mux2(in0.getWidth)
m.io.sel := sel.toBool()
m.io.in0 := in0
m.io.in1 := in1
m.io.out
}
}
我写的Tester scala类:
/chisel-template/src/test/scala/Mux4Test.scala
import Chisel.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
class Mux4Test(c: Mux4) extends PeekPokeTester(c) {
val sel = 3
val (in0, in1, in2, in3) = (5, 7, 11, 15)
poke(c.io.sel, sel)
poke(c.io.in0, in0)
poke(c.io.in1, in1)
poke(c.io.in2, in2)
poke(c.io.in3, in3)
step(1)
System.out.println("Circuit: "+peek(c.io.out)
+" Expected: "+TestMux4.result(sel, in0, in1, in2, in3))
}
object TestMux4{
def result(sel: Int, in0: Int, in1: Int, in2: Int, in3: Int): Int = {
val out = sel match{
case 0 => in3
case 1 => in2
case 2 => in1
case 3 => in0
}
out
}
}
class Mux4Tester extends ChiselFlatSpec {
behavior of "Mux4"
backends foreach {backend =>
it should s"do Mux4 $backend" in {
Driver(() => new Mux4(4), backend)(c => new Mux4Test(c)) should be (true)
}
}
}
输出
的重要部分STEP 0 -> 1
Circuit: 0 Expected: 5
Mux4类(Circuit)返回0作为输出,而应该是5,因为选择过程如下:
00 -> io.out = in3 = 15
01 -> io.out = in2 = 11
10 -> io.out = in1 = 7
11 -> io.out = in0 = 5
在 Mux4Test.scala 类中我写了 val sel = 3。它的位表示是 11,因此我希望 in0 = 5。
我哪里错了?
【问题讨论】:
标签: scala module riscv mux chisel