【发布时间】:2018-01-31 14:51:03
【问题描述】:
我正在尝试在 SublimeText3 中过滤我的构建系统的输出。
首先,谁能解释一下两者的区别:
"file_regex": "",
"line_regex": "",
我想从这个示例输出中捕获以下行:
Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]
.
VHDL/Verilog/EDIF/SystemC Simulator build 10.3.3558.6081
(c) 1997-2016 Aldec, Inc. All rights reserved.
License Number 0
Welcome to VSIMSA!
This message was printed from `startup.do' macro file.
# creating library
alib work
ALIB: Library `work' attached.
Compile success 0 Errors 0 Warnings Analysis time : 31.0 [ms]
Compile Package "BT601_cfg"
Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]
# starting simulation with tb_top as the top level module
# asim fpc_tb
# running the simulation
# run 1000us
echo hi
hi
quit
【问题讨论】:
-
我的正则表达式是以下atm:^编译成功[0-9]+错误[0-9]+警告分析时间:[0-9]+\.[0-9]+[毫秒]
标签: regex build sublimetext3