VHDL 代码综合错误

Question

我编写了一个 VHDL 代码来实现 PWM 控制器的功能。我已经模拟成功，结果符合预期。我还检查了合成的语法，但它显示了任何错误。当我使用 XILINX ISE 12.4 合成它时，它没有合成并且错误状态

"ERROR:Xst:827 - line 67: Signal tmp_PC cannot be synthesis, bad synchronous description. 您用来描述同步元素（寄存器、内存等）的描述风格在当前软件版本中不受支持。”

--library UNISIM;
--use UNISIM.VComponents.all;

entity CONTROLLER is
PORT(

    CLK:    IN  STD_LOGIC;
    VOUT: IN  STD_LOGIC;
    M1:   OUT STD_LOGIC:='0';
    M2:   OUT STD_LOGIC:='0'

);


end CONTROLLER;

architecture Behavioral of CONTROLLER is

    SIGNAL VREF:        STD_LOGIC_VECTOR(7 DOWNTO 0):="01000000";
    SIGNAL V_ERR:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM_NEW:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL COUNT:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL COUNT2:          STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP1:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP2:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP3:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL FEED_BACK:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL REG:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM_COUNT:       STD_LOGIC_VECTOR(7 DOWNTO 0):="10000000";

BEGIN

PROCESS(CLK)

BEGIN

    IF(RISING_EDGE(CLK) AND COUNT2<"10000000")THEN
            COUNT <= COUNT+'1';
    END IF;

    IF(RISING_EDGE(CLK) AND COUNT2>="10000000")THEN
        COUNT <= COUNT+'1';
    END IF;

    IF (COUNT>"00000101" AND COUNT<"01111000") THEN
        IF(RISING_EDGE(CLK))THEN
            IF (VOUT='0') THEN
                FEED_BACK<= FEED_BACK+'1';
            END IF;
        END IF;
    END IF;   

    IF (COUNT>"01111000" AND COUNT<"01111100")THEN
        REG<=FEED_BACK;
        TEMP1<=VREF-REG;
        IF(TEMP1>"01000000") THEN
           TEMP2<=TEMP1+"11111111";
            V_ERR<=TEMP2+'1';
        END IF;
        IF (TEMP1<"01000000") THEN
                V_ERR<=TEMP1;
        END IF;

        PWM<=V_ERR+VREF;

        IF (PWM>"11000000")THEN
             PWM<="11000000";
        IF(PWM<"00001010")THEN
            PWM<="00001010";

        END IF;
        END IF;

    END IF;

    PWM_NEW<= PWM;

   IF (RISING_EDGE(CLK))THEN
        IF(COUNT="01111111")THEN
            COUNT<="00000000";
            FEED_BACK<="00000000";
        END IF;
    END IF;

    IF(RISING_EDGE(CLK))THEN
        COUNT2 <= COUNT2+ '1';
    END IF;

   IF(COUNT>"00000000" AND COUNT<("00000010"))THEN
        IF(RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='0';
        END IF;
   END IF;

    IF(COUNT>("00000010") AND COUNT<("00000010"+PWM_NEW))THEN
        IF(RISING_EDGE(CLK)) THEN
            M1<='1';
            M2<='0';
        END IF;
   END IF;

    IF(COUNT>("00000010"+PWM_NEW) AND COUNT<("00000100"+PWM_NEW))THEN
        IF ( RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='0';
        END IF;
    END IF;

    IF(COUNT>("00000100"+PWM_NEW) AND COUNT<("10000000"))THEN
        IF (RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='1';
        END IF;
    END IF;

    IF (COUNT=("10000000"))THEN
        IF (RISING_EDGE(CLK)) THEN
            COUNT2<="10000001";
        END IF;
    END IF;

END PROCESS;
end Behavioral;`

我尝试查找错误消息并得到不同的答案。可能的原因似乎 1：不符合合成模板的“IF”嵌套不当。 2：使用“risisng_edge(clk)”代替通常的“(clk'event and clk='1')”。

我仍然不完全确定可能是什么问题。如果有人可以提出我忽略的可能错误，那将非常有帮助。

Answer 1

为了被综合工具识别，您的进程必须有一个单个 if rising_edge(clk) 块。

修改你的代码应该很容易，除了reg <= feed_back;的块

如果此特定部分对异步行为进行建模，则将其移至组合过程。

关于您列出的可能原因 1. 和 2.，您的代码在这两个方面都可以：嵌套可以（在语法上）并且您对 rising_edge 的使用可以。

Answer 2

看起来你可以编写完整的同步代码

process(clk)
begin
    -- put your asyncron code here if needed
    if(rising_edge(clk)) then
      if(reset = '1') then
      -- if you like to implement a synchron reset
      else
      -- all your synchron code e.g.

         if (COUNT2 >= "10000000") then
            COUNT <= COUNT+'1';
         end if;

         if (COUNT > ("00000100"+PWM_NEW)) AND (COUNT < "10000000") then
            M1 <= '0';
            M2 <= '1';
         end if;
         .
         .
         .

      end if;
   end if;
   -- put your asyncron code here if needed
end process;

不要使用 unisim 库......你可以用这两者做任何事情

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

有标准化的。

为了更清楚一点，你可以用十六进制写法

if (COUNT2 >= x"80") then -- 80 hex = 124 dec
   COUNT <= COUNT+'1';
end if;

或者你可以使用无符号信号

SIGNAL COUNT:       unsigned (7 DOWNTO 0) := (others => '0'); -- same as "000000000" but looks better

if (COUNT2 >= 128) then
   COUNT <= COUNT + '1';
end if;

计算不是问题，例如

if (COUNT > ("00000100"+PWM_NEW)) AND (COUNT < "10000000") then
   M1 <= '0';
   M2 <= '1';
end if;

会

 if (COUNT > (unsigned(PWM_NEW) + 4)) AND (COUNT < 128) then
    M1 <= '0';
    M2 <= '1';
 end if;