通用记录（通过 vhdl 2008 通用包尝试）

Question

我想为组件C编写一个库，该组件在内部分为两个子组件c1和c2，它们可以通过泛型进行配置。子模块应通过记录连接，这取决于泛型。该记录也应在组件内使用。通常我会在package 中实例化记录，并在子组件的文件和组件的文件中使用包。由于它是通用的，我认为使用通用包 (VHDL-2008) 可能会提供解决方案。

问题是我还需要从子组件中访问记录。为此，我需要use thePackage，但是要使用通用包，我需要传递初始值（据我所知）。

所以我尝试了（注意：我不是在这里处理记录，我只是想从一个通用组件访问一个通用包，我用组件的参数参数化（？）包）：

entity genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
end entity;

architecture behav of genericPackagePart is
    package test is new work.genericPackage
    generic map(
        genSize => outputValue
    );

    use work.test.all;
begin
    result <= dummy;  -- dummy is a constant from genericPackage set to the value genSize (generic parameter)
end architecture;

但是我从 modelsim 收到以下错误：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(17): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(17): Unknown expanded name.
** Error: genericPackagePart.vhd(19): (vcom-1136) Unknown identifier "dummy".
** Error: genericPackagePart.vhd(20): VHDL Compiler exiting

更新： 我尝试将genericPackagePart 包装在一个泛型包中，并使用泛型从该包中实例化genericPackage，这也不起作用。

流程应该是：

• Testbench => 使用通用参数实例化 genericPackagePart 和 genericPackage
• 测试平台中的记录来自genericPackage
• 内部genericPackagePartgenericPackage被实例化，参数传递给genericPackagePart
• 记录在genericPackagePart内可用

Modelsim 给出了错误（test 是我在genericPackagePart 中给genericPackage 的参数化实例起的名称，这是来自genericPackagePart 的编译）：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(11): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(11): Unknown expanded name.
** Error: genericPackagePart.vhd(13): near "entity": expecting END

---

我查看了Passing Generics to Record Port Types，但这并没有解决基于泛型的包实例化问题

---

为了完整起见，这里是包和测试台：

包装：

package genericPackage is
    generic(genSize : integer := 1);

    constant dummy : integer := genSize;
end package;

测试台：

package myGenericPackage is new work.genericPackage
generic map(
    genSize => 5
);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal : integer;
    signal testsignal2 : integer;
    signal dummy : integer := 12;

    component genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
    end component;
begin
    test : process is
    begin
        wait for 20 ns;
        testsignal <= dummy;
        wait for 20 ns;
        testsignal <= work.myGenericPackage.dummy;
        wait;
    end process;

    testPart: genericPackagePart
        port map(result => testsignal2)
        generic map(outputValue => 128);
end architecture;

Answer 1

我认为问题在于你的包test需要定义在实体区，而不是架构区：

package genericPackage is
    generic(genSize : integer := 1);
    constant dummy : integer := genSize;
end package;
entity genericPackagePart is
    generic(outputValue : integer);
    port(result : out integer);

    -- *** Generic package instantiated here ***
    package test is new work.genericPackage
       generic map(genSize => outputValue);

end entity;
architecture behav of genericPackagePart is
    use test.all;
begin
    result <= dummy;  -- dummy is from genericPackage (=genSize)
end architecture;

这是我测试它的方法（基于您的测试平台）：

package myGenericPackage is new work.genericPackage
   generic map(genSize => 5);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal  : integer;
    signal testsignal2 : integer;
begin
    test : process is
    begin
        testsignal <= work.myGenericPackage.dummy;
        wait for 20 ns;

        assert testsignal = work.myGenericPackage.dummy 
            report "test signal should be work.myGenericPackage.dummy" 
            severity error;
        assert testsignal2 = 128 report "testsignal2 /= 128" severity error;
        report "testsignal = " & integer'image(testsignal);
        report "testsignal2 = " & integer'image(testsignal2);
        report "Finished";
        wait;
    end process;

    testPart : entity work.genericPackagePart
        generic map(outputValue => 128)
        port map(result         => testsignal2);
end architecture;

使用 Modelsim 10.2 编译和模拟：

vcom -2008 genpacktest.vhd; vsim -c genericPackageTestbench -do "run -all; quit"

哪些报告：

# Loading std.standard
# Loading work.genericpackage
# Loading work.mygenericpackage
# Loading work.genericpackagetestbench(testbench)
# Loading work.genericpackagepart(behav)
# run -all 
# ** Note: Finished
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal = 5
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal2 = 128
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
#  quit