时钟门控verilog代码无法正常工作

Question

我正在尝试编写一个时钟门控逻辑，它只允许数据在 posedge write_clk_en 处通过。代码在 EDA 操场上正确编译，但输出不符合预期。所以根据代码，

@ (posedge write_clk_en)begin
 data_in[3] <= 1'b1;
end

在这种情况下 write_clk_en 被禁用，因此 data_in[3] NBA 应该停止并等待下一个有效的 posedge（这里是 write_clk_en 的下一个 posedge），应该写入 data_in[3]。但这并没有发生，而是门控时钟周期也在考虑之中，即使 write_clk_en 被门控到第 4 个脉冲，NBA 分配也会发生。可能是什么问题？.波形显示在这里。

sv 代码：

module tb;

logic [4:0]  data_in;
logic  write_clk;
logic  write_clk_en;
logic write_clk_mod;  
logic [5:0] write_clk_init;

always//write_clk 500M
  begin
        write_clk  =0;
    #10 write_clk = 1;
    #10 write_clk = 0;
  end


initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 $finish;
end  

initial begin
data_in=5'b00000;
write_clk_init = 6'b000000;
write_clk_mod=0;
end

initial begin
write_clk_init =6'b110111;
end

initial begin
repeat (3) begin
@(posedge write_clk)begin
if(write_clk_init[0]==1 || write_clk_init[0]==0)
write_clk_mod<=write_clk_init[0];
end
@(posedge write_clk)begin
if(write_clk_init[1]==1 || write_clk_init[1]==0)
write_clk_mod<=write_clk_init[1];
end
@(posedge write_clk)begin
if(write_clk_init[2]==1 || write_clk_init[2]==0)
write_clk_mod<=write_clk_init[2];
end
@(posedge write_clk)begin
if(write_clk_init[3]==1 || write_clk_init[3]==0)
write_clk_mod<=write_clk_init[3];
end
@(posedge write_clk)begin
if(write_clk_init[4]==1 || write_clk_init[4]==0)
write_clk_mod<=write_clk_init[4];
end
@(posedge write_clk)begin
if(write_clk_init[5]==1 || write_clk_init[5]==0)
write_clk_mod<=write_clk_init[5];
end
end
end

  always @ (*) begin 
  write_clk_en  = write_clk & write_clk_mod;
end

initial begin 

@ (posedge write_clk_en)begin
data_in[0] <= 1'b1;
end
@ (posedge write_clk_en)begin
data_in[1] <= 1'b1;
end
@ (posedge write_clk_en)begin
 data_in[2] <= 1'b1;
 end
@ (posedge write_clk_en)begin
 data_in[3] <= 1'b1;
end
@ (posedge write_clk_en)begin
data_in[4] <= 1'b1;
end

end


endmodule

Answer 1

在初始块内，将您的 NBA 更改为 BA。 NBA 只能在 always @(posedge clocksignal) block 中使用

还要考虑到，在模拟中，@(posedge clocksignal) 块（没有保留字 always）被视为延迟（等到上升沿 clk 事件发生，然后继续模拟）。顺便说一句，你在最初的陈述中写了这些块，我不确定你是否知道它们的真实行为。我重写了那些@(posedge) 块以使模拟流程更加清晰。

我还将您的一些初始块合并为一个。您拥有的每个初始块都同时启动（模拟时间 0）。特别是，write_clk_init 被分配在两个不同的初始块中。

此编辑后的代码按预期工作。它也可以在https://www.edaplayground.com/x/3VYk 获得。

module tb;
  reg [4:0]  data_in;
  reg  write_clk;
  reg  write_clk_en;
  reg write_clk_mod;  
  reg [5:0] write_clk_init;

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    #10000 $finish;
  end  

  initial begin
    data_in = 5'b00000;
    write_clk_init = 6'b110111;
    write_clk_mod = 0;
    write_clk = 0;

    repeat (3) begin
      @(posedge write_clk);
      if(write_clk_init[0]==1 || write_clk_init[0]==0)
          write_clk_mod = write_clk_init[0];

      @(posedge write_clk);
      if(write_clk_init[1]==1 || write_clk_init[1]==0)
          write_clk_mod = write_clk_init[1];

      @(posedge write_clk);
      if(write_clk_init[2]==1 || write_clk_init[2]==0)
          write_clk_mod = write_clk_init[2];

      @(posedge write_clk);
      if(write_clk_init[3]==1 || write_clk_init[3]==0)
          write_clk_mod = write_clk_init[3];

      @(posedge write_clk);
      if(write_clk_init[4]==1 || write_clk_init[4]==0)
          write_clk_mod = write_clk_init[4];

      @(posedge write_clk);
      if(write_clk_init[5]==1 || write_clk_init[5]==0)
          write_clk_mod = write_clk_init[5];
    end
  end

  always @* begin 
    write_clk_en  = write_clk & write_clk_mod;
  end

  initial begin 
    @(posedge write_clk_en);
    data_in[0] = 1'b1;

    @(posedge write_clk_en);
    data_in[1] = 1'b1;

    @(posedge write_clk_en);
    data_in[2] = 1'b1;

    @(posedge write_clk_en);
    data_in[3] = 1'b1;

    @(posedge write_clk_en);
    data_in[4] = 1'b1;
  end

  always begin
    write_clk = #10 ~write_clk;
  end      
endmodule