端口映射内存组件不起作用答案

【问题标题】：Port Mapping memory components not working端口映射内存组件不起作用
【发布时间】：2014-07-18 03:03:59
【问题描述】：

我正在使用 Quartus II，我需要从 128x1B 的 8 个组件中创建一个 256 x 4B (1KB) 内存，但我不是 vhdl 的初学者。

这是使用 MegaWizard Quartus II 插件创建的 128x1B 组件（这不是问题所在）：

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY RAM_128B_MegaWizard IS
PORT
(
    address     : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    clock       : IN STD_LOGIC  := '1';
    data        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    wren        : IN STD_LOGIC ;
    q       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END RAM_128B_MegaWizard;

ARCHITECTURE SYN OF ram_128b_megawizard IS

SIGNAL sub_wire0    : STD_LOGIC_VECTOR (7 DOWNTO 0);

COMPONENT altsyncram
GENERIC (
    clock_enable_input_a        : STRING;
    clock_enable_output_a       : STRING;
    intended_device_family      : STRING;
    lpm_hint        : STRING;
    lpm_type        : STRING;
    numwords_a      : NATURAL;
    operation_mode      : STRING;
    outdata_aclr_a      : STRING;
    outdata_reg_a       : STRING;
    power_up_uninitialized      : STRING;
    widthad_a       : NATURAL;
    width_a     : NATURAL;
    width_byteena_a     : NATURAL
);
PORT (
        wren_a  : IN STD_LOGIC ;
        clock0  : IN STD_LOGIC ;
        address_a   : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
        q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        data_a  : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN
q    <= sub_wire0(7 DOWNTO 0);

altsyncram_component : altsyncram
GENERIC MAP (
    clock_enable_input_a => "BYPASS",
    clock_enable_output_a => "BYPASS",
    intended_device_family => "Cyclone II",
    lpm_hint => "ENABLE_RUNTIME_MOD=NO",
    lpm_type => "altsyncram",
    numwords_a => 128,
    operation_mode => "SINGLE_PORT",
    outdata_aclr_a => "NONE",
    outdata_reg_a => "UNREGISTERED",
    power_up_uninitialized => "FALSE",
    widthad_a => 7,
    width_a => 8,
    width_byteena_a => 1
)
PORT MAP (
    wren_a => wren,
    clock0 => clock,
    address_a => address,
    data_a => data,
    q_a => sub_wire0
);

END SYN;

现在问题来了。我正在尝试使用端口映射来实例化内存组件，但出现以下错误

Error (10500): VHDL syntax error at RAM_256x4B.vhd(50) near text "1.1";  expecting  "end", or "(", or an identifier, or a concurrent statement
Error (10500): VHDL syntax error at RAM_256x4B.vhd(51) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(53) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(55) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(57) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(60) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(62) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(64) near text ";";  expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(66) near text ";";  expecting "<="

这是代码。我的地址必须为 10 位，并且我正在使用解码器和多路复用器通过包。

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

library work;
use work.RAM_128B_MegaWizard_package.all;
use work.dec1to2_package.all;
use work.mux2to1_package.all;

entity RAM_256x4B is 
generic( 
        depth : integer range 1 to 10 := 10; 
        width: integer range 1 to 32 := 32; 
        init_file : string := "init_file2.mif"); 
        -- .mif filename 

port(Clock : in std_logic; 
     WrEn: in std_logic; 
    -- write control signal 
     Address : in std_logic_vector(depth-1 downto 0); 
    -- read and write addresses 
     data : in std_logic_vector(width-1 downto 0); 
    -- data to be written 
     DataOut : out std_logic_vector(width-1 downto 0)); 
    -- memory read output 
end RAM_256x4B;

architecture behavior of RAM_256x4B is

signal dOut0: std_logic_vector(width-1 downto 0);
signal dOut1: std_logic_vector(width-1 downto 0);
signal En: std_logic_vector(0 to 1);

begin

    decoder: dec1to2 port map (Address(depth-3), WrEn, En);

    1.1: RAM_128B_MegaWizard port map
        (Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));
    1.2: RAM_128B_MegaWizard port map
        (Clock, En(0), Address(depth-4 downto 0), data(23 downto 16), dOut0(23 downto 16));
    1.3: RAM_128B_MegaWizard port map
        (Clock, En(0), Address(depth-4 downto 0), data(15 downto 8), dOut0(15 downto 8));       
    1.4: RAM_128B_MegaWizard port map
        (Clock, En(0), Address(depth-4 downto 0), data(7 downto 0), dOut0(7 downto 0));

    2.1: RAM_128B_MegaWizard port map
        (Clock, En(1), Address(depth-4 downto 0), data(width-1 downto 24), dOut1(width-1 downto 24));
    2.2: RAM_128B_MegaWizard port map
        (Clock, En(1), Address(depth-4 downto 0), data(23 downto 16), dOut1(23 downto 16));
    2.3: RAM_128B_MegaWizard port map
        (Clock, En(1), Address(depth-4 downto 0), data(15 downto 8), dOut1(15 downto 8));       
    2.4: RAM_128B_MegaWizard port map
        (Clock, En(1), Address(depth-4 downto 0), data(7 downto 0), dOut1(7 downto 0));         

    mux: mux2to1 port map (dOut0, dOut1, Address(depth-3),DataOut);

end behavior;

我知道它不完整，但无论我做什么编译都会给我同样的错误。即使开始和结束架构之后的部分只是

1.1: RAM_128B_MegaWizard port map
        (Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));

同样的事情也会发生。

我知道端口映射不能在进程内使用，但是带有进程的组件（128x1B）也不能被端口映射？我如何结合这些组件来制作我想要的东西？

【问题讨论】：

标签： vhdl

【解决方案1】：

在我看来，您在通过引用进行端口映射时遇到了问题。这是您要实例化的组件：

address     : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock       : IN STD_LOGIC  := '1';
data        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren        : IN STD_LOGIC ;
q       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

所以如果你是通过引用做的，你应该有这个实例化：

 inst_1_1 : RAM_128B_MegaWizard port map
    (Address(depth-4 downto 0), Clock, data(width-1 downto 24), En(0), dOut0(width-1 downto 24));

注意信号的位置。这就是为什么我更喜欢做显式端口映射，你会犯更少的错误。

我也不确定你的实例化名称有什么限制，但 1.1 对我来说似乎不是一个好名字。尝试以字母开头且仅包含下划线而非句点的内容。

【讨论】：

感谢您发现第一个错误，我自己应该看到的。真正的问题是实例化名称，就像您也指出的那样。我现在遇到了其他问题，我应该能够解决，但那个问题已经解决了。再次感谢

【解决方案2】：

标签必须是标识符。这些会导致 Error (10500) VHDL... 错误。

基本标识符：

 basic_identifier ::=
     letter  { [ underline ] letter_or_digit }

 letter_or_digit ::=  letter | digit

 letter ::=  upper_case_letter | lower_case_letter

或扩展标识符：

 extended_identifier ::=
    \ graphic_character { graphic_character } \

在您的情况下，标签（1.1、1.2 等）需要以字母开头，有点像 Russel 在他的回答中偶然展示的那样，除了在实例化它们的端口接口中的位置关联不正确之外。

解决这两个问题。

【讨论】：