程序计数器不递增答案

【问题标题】：Program Counter not incrementing程序计数器不递增
【发布时间】：2022-01-18 02:15:13
【问题描述】：

我正在尝试为 RISC 处理器创建程序计数器，但我不确定为什么测试台没有按预期工作。测试台的编写方式可能有问题，但我似乎找不到。在测试台的模拟中，计数器值似乎没有像预期的那样增加一。任何帮助将不胜感激。

module ProgramCounter 

// identify inputs and outputs, define if the input/output is signed. 
(
input Clock,
input logic Reset,
input logic [15:0] LoadValue,
input logic LoadEnable,
input logic signed [8:0] Offset,
input logic OffsetEnable,
output logic signed [15:0] CounterValue
);

// Clock, Reset, LoadEnable and OffsetEnable triggered at positive edge of clock.
    always_ff@(posedge Clock)
    begin
        if (Reset) CounterValue <= '0; //if reset is TRUE, CounterValue is zero.
        else if (LoadEnable) CounterValue <= LoadValue; //if LoadEnable is TRUE, CounterValue is equal to LoadValue.
        else if (OffsetEnable) CounterValue <= CounterValue + Offset;//if OffsetEnableEnable is TRUE, CounterValue is CounterValue plus Offset.
        else CounterValue <= CounterValue + 1;//otherwise, CounterValue increases with the clock.
    end


endmodule

// ProgramCounterTestBench
//
//
// This module implements a testbench for 
// the Program Counter 
//

module ProgramCounterTestBench();

    // These are the signals that connect to 
    // the program counter
    logic               Clock = '0;
    logic               Reset;
    logic signed       [15:0]   LoadValue;
    logic               LoadEnable;
    logic signed  [8:0] Offset;
    logic                   OffsetEnable;
    logic signed  [15:0]    CounterValue;

    // this is another method to create an instantiation
    // of the program counter
    ProgramCounter uut
    (
        .Clock,
        .Reset,
        .LoadValue,
        .LoadEnable,
        .Offset,
        .OffsetEnable,
        .CounterValue
    );
    

    default clocking @(posedge Clock);
    endclocking
        
    always  #10  Clock++;

    initial
    begin
        Reset = 0;
        LoadEnable = 0;
        OffsetEnable = 0;
        LoadValue = 16'b0000000000000000;
        Offset = 9'b000000000;
        CounterValue = 16'b0000000000000010;

        #60

        #10     Reset = 0;
                LoadEnable = 1;
                LoadValue = 16'b0101010101010101;

        #10     Reset = 1;
                LoadEnable = 0;
                OffsetEnable = 0;
                LoadValue = 16'b0101010101010101;
                Offset = 9'b000000000;

        #10     Reset = 0;
                LoadEnable = 1;
                OffsetEnable = 0;
                LoadValue = 16'b0101010101010101;
                Offset = 9'b000000000;  

        #10     Reset = 0;
                LoadEnable = 0;
                OffsetEnable = 0;
                                        

        #10     Reset = 0;
                LoadEnable = 0;
                OffsetEnable = 1;
                LoadValue = 16'b0101010101010101;
                Offset = 9'b101000000;
    end
endmodule

【问题讨论】：

标签： verilog test-bench

【解决方案1】：

我在使用多个模拟器时遇到编译错误。例如，Cadence 模拟器会生成此错误：

        .CounterValue
                    |
xmelab: *E,ICDPAV : Illegal combination of driver and procedural assignment to variable CounterValue detected (procedural assignment found in initial block

注册免费帐户后，您可以在edaplayground 上的多个模拟器上试用您的代码。

问题出在测试台上：

    CounterValue = 16'b0000000000000010;

测试台中的CounterValue信号有多个驱动：

实例输出端口连接
initial 块中的上述行

您应该只允许实例驱动此信号。当您删除上面的行时，您将看到计数器按预期增加。

【讨论】：