【发布时间】:2022-01-03 03:17:24
【问题描述】:
代码不会太长,所以我把完整的代码贴出来。
// Code your design here
module temp;
typedef enum logic[15:0]
{
ADD = 16'h0000,
SUB = 16'h0001
} my_opcode_t;
typedef enum logic[15:0]
{
REG = 16'h0000,
MEM = 16'h0001
} my_dest_t;
typedef struct packed
{
my_opcode_t opcode; // 16-bit opcode, enumerated type
my_dest_t dest; // 16-bit destination, enumerated type
logic [15:0] opA;
logic [15:0] opB;
} my_opcode_struct_t;
my_opcode_struct_t cmd1;
typedef union packed
{
my_opcode_struct_t opcode_s; //"fields view" to the struct
logic[1:0][31:0] dword; // "dword view" to the struct
} my_opcode_union_t;
my_opcode_union_t cmd2;
initial begin
$display("cmd1 = %p",cmd1);
$display("cmd2 = %p", cmd2);
// Access opcode_s struct fields within the union
cmd2.opcode_s.opcode = ADD;
cmd2.opcode_s.dest = REG;
cmd2.opcode_s.opA = 16'h0001;
cmd2.opcode_s.opB = 16'h0002;
$display("cmd1 = %p",cmd1);
$display("cmd2 = %p", cmd2);
// Access dwords struct fields within the union
cmd2.dword[1] = 32'h0001_0001; // opcode=SUB, dest=MEM
cmd2.dword[0] = 32'h0007_0008; // opA=7, opB=8
$display("cmd2 = %p", cmd2);
end
endmodule
来源:https://www.verilogpro.com/systemverilog-structures-unions-design/
输出:
我在 EDA 操场上运行了这段代码。我不明白为什么会显示”
cmd2='{opcode_s:'{opcode:SUB, dest:MEM, opA:'h7,opB:'h8}}
我期待,它会打印 dword 值。
我对工会的理解中缺少什么?
是不是因为我们没有使用cmd2.dword[0] 或cmd2.dword[1] 打印一些垃圾值?
【问题讨论】:
标签: oop enums system-verilog unions