无法运行 AND 银行测试台？

Question

这是我的代码：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY AND_Bank_Test IS
END AND_Bank_Test;

ARCHITECTURE behavior OF AND_Bank_Test IS 

 -- Component Declaration for the Unit Under Test (UUT)

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(7 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(7 downto 0)
    );
END COMPONENT;


   --Inputs

signal Input : std_logic_vector(7 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(7 downto 0);

-- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 


BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

   -- Stimulus process

   stim_proc: process
    begin       
-- hold reset state for 100 ns.

    wait for 100 ns;    

    Input <= "00000001" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "00111011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "01110111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110000" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "11110011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "01110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "11111111" ; AND_Bit <= 1; 
    wait for 100 ns;    
wait;
end process;

END;

这是我得到的错误：

Type std_logic does not match with the integer literal (this refers to Input <= "00000001" ; AND_Bit <= 0; )

我已经用这个替换了我的代码：

ENTITY AND_Bank_Test IS END AND_Bank_Test；

AND_Bank_Test 的架构行为是

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(15 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(15 downto 0)
    );

结束组件；

--输入

signal Input : std_logic_vector(15 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(15 downto 0);

开始

-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

-- 刺激过程

stim_proc：进程 开始
-- 保持复位状态 100 ns。

    wait for 100 ns;    

    Input <= "0000000000000001" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000000111011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000001110111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110000" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000011110011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000001110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000011111111" ; AND_Bit <= '1'; 
    wait for 100 ns;    

等待； 结束进程；

结束；

这是运行 AND 银行测试的正确方法吗？ 为什么不能只用 8 位运行？

Answer 1

你需要使用单引号，例如：

Input <= "00000001" ; AND_Bit <= '0';

如果您不使用单引号，则假定您将整数值分配给 AND_Bit，这就是它给您错误的原因。

Answer 2

关于您的错误，AND_Bit 是 std_logic。您必须在测试台中写入 AND_BIT <= '0'; 而不是 AND_BIT <= 0; 这就是模拟器将 0 视为整数而不是位的原因。对于 cmets 中的第二个错误，您更改了 IN and OUT 的大小，它是 16 位，但在测试台中，您提供 8 位作为输入。所以相应地改变大小。