【发布时间】:2021-04-26 20:21:15
【问题描述】:
entity LFSR is
Port ( clk : in STD_LOGIC;
en: in STD_LOGIC;
reset: in STD_LOGIC;
output_lfsr: out STD_LOGIC_VECTOR(2 downto 0)
);
end LFSR;
architecture Behavioral of LFSR is
signal lfsr : std_logic_vector(2 downto 0);
constant poly : std_logic_vector(2 downto 0) := "011";
begin
process(clk, reset, lfsr)
variable ext_inbit: std_logic_vector(2 downto 0);
variable inbit: std_logic;
begin
inbit:=lfsr(2); -- preia valoarea iesirii Q2
for i in 0 to 2 loop
ext_inbit(i):=inbit;
end loop;
if (reset='1') then
lfsr<="111";
elsif (clk'event and clk='1') then
if(en='1') then
lfsr<=(lfsr(1 downto 0) & '0') xor (ext_inbit and poly);
end if;
end if;
end process;
output_lfsr <= lfsr;
end Behavioral;
【问题讨论】:
标签: vhdl