vhdl 错误：靠近文本“<=”；期待“（”，或标识符，或一元运算符答案

【问题标题】：vhdl error: near text "<="; expecting "(", or an identifier, or unary operatorvhdl 错误：靠近文本“<=”；期待“（”，或标识符，或一元运算符
【发布时间】：2021-05-18 21:24:38
【问题描述】：

我想将二进制转换为十进制，所以我使用了to_integer。我打算先输入X <= 10110101，然后输入M <= 181，然后用百、十、单位分隔整数，我打算M_100 <= 1、M_10 <= 8、M_1 <= 1

我还需要把十进制转成二进制，我打算temp1 <= 0001，temp2 <= 1000，temp3 <= 0001

请告诉我出现如下代码错误的原因。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity TEST is
    port(X: in std_logic_vector(7 downto 0);
          M_100: buffer integer;
          M_10: buffer integer;
          M_1: buffer integer;
          M: buffer integer;
         Y: out std_logic_vector(2 downto 0));
end TEST;

architecture EX of TEST is

signal temp1: std_logic;
signal temp2: std_logic;
signal temp3: std_logic;

begin

X <= "00110101";
M <= to_integer(unsigned(X)); 
M_100 <= M/100;
    with M_100 select temp1 <= "0000" when 0,
                                    <= "0001" when 1,
                                    <= "0010" when 2,
                                    <= "0011" when 3,
                                    <= "0100" when 4,
                                    <= "0101" when 5,
                                    <= "0110" when 6,
                                    <= "0111" when 7,
                                    <= "1000" when 8,
                                    <= "1001" when 9;
M_10 <= (M - (M_100*100))/10;
    with M_10 select temp2 <= "0000" when 0,
                                    <= "0001" when 1,
                                    <= "0010" when 2,
                                    <= "0011" when 3,
                                    <= "0100" when 4,
                                    <= "0101" when 5,
                                    <= "0110" when 6,
                                    <= "0111" when 7,
                                    <= "1000" when 8,
                                    <= "1001" when 9;
M_1 <= (M - (M_100*100) - (M_10*10));   
    with M_1 select temp3 <= "0000" when 0,
                                    <= "0001" when 1,
                                    <= "0010" when 2,
                                    <= "0011" when 3,
                                    <= "0100" when 4,
                                    <= "0101" when 5,
                                    <= "0110" when 6,
                                    <= "0111" when 7,
                                    <= "1000" when 8,
                                    <= "1001" when 9;       
Y(2) <= temp1, Y(1) <= temp2, Y(0) <= temp3;

end EX;

错误代码：VHDL 语法错误“接近文本”

【问题讨论】：

VHDL syntax error at <location> near text <text> (ID: 10500)。 IEEE Std 1076-1993 9.5.2 选定信号分配“selected_signal_assignment ::= 带有表达式选择目标 when 选择 , } 波形 when 选择”注意<= 的单次出现。还有其他语义错误。
见Convert 8bit binary number to BCD in VHDL。

标签： vhdl

【解决方案1】：

我看到了 3 个问题。

1：temp1、2 和 3 是 std_logic。他们不接受向量分配。你可能在 std_logic_vector 之后。

2: 你的 with/select 的语法是错误的。它应该是这样的：

with M_100 select temp1 <= "0000" when 0,
                           "0001" when 1,
                           "0010" when 2,
                           "0011" when 3,
                           "0100" when 4,
                           "0101" when 5,
                           "0110" when 6,
                           "0111" when 7,
                           "1000" when 8,
                           "1001" when 9;

3：通常最好指定一个默认条件，以避免闩锁或未定义的逻辑。

with M_100 select temp1 <= "0000" when 0,
                           "0001" when 1,
                           "0010" when 2,
                           "0011" when 3,
                           "0100" when 4,
                           "0101" when 5,
                           "0110" when 6,
                           "0111" when 7,
                           "1000" when 8,
                           "1001" when 9,
                           "0000" when others;

【讨论】：