Verilog：转换后的整数不适用于 For 循环

Question

我正在用 Verilog 编写一个程序，它接受一个二进制值，将其转换为整数，然后打印“Hello, World!”那个次数。

但是，每当我运行程序时，都没有显示 Hello, World。代码如下：

// Internal Variable
wire [0:4] two_times_rotate;

// Multiply the rotate_imm by two (left shift)
assign {two_times_rotate} = rotate_imm << 1;
integer i, times_rotated;

// Convert two_times_rotate into an integer
always @( two_times_rotate )
begin
  times_rotated = two_times_rotate;
end

initial 
begin

for (i = 0; i < times_rotated; i = i + 1)
begin
  $display("Hello, World");
end

end

assign {out} = in;
 endmodule

我尝试使用以下 for 循环：

for (i = 0; i < 7; i = i + 1)

这个打印 Hello, World 七次，就像它应该的那样。

*更新*

到目前为止，这就是我的代码中的内容。我正在尝试做一个比较位的 for 。它仍然无法正常工作。如何以一种可以在 for 循环的比较中使用的方式将二进制完全转换为整数？

 module immShifter(input[0:31] in, input[0:3] rotate_imm, 
              output[0:31] out);

 // Internal Variable
 wire [0:4] two_times_rotate;
 reg [0:4] i;

 // Multiply the rotate_imm by two (left shift)
 assign {two_times_rotate} = rotate_imm << 1;
 integer times_rotated, for_var;

 // Convert two_times_rotate into an integer
 always @( two_times_rotate )
 begin
    assign{times_rotated} = two_times_rotate;
 end

 initial 
 begin

 assign{i} = 5'b00000;
 assign{for_var} = times_rotated;
 for (i = 5'b00000; i < times_rotated; i = i + 5'b00001)
 begin
   $display("Hello, World");
 end

 end

 assign {out} = in;
endmodule 

Answer 1

times_rotated 是 32'bX 在评估 for 循环时的时间 0。 for 循环正在检查i < 32'bX，这是错误的。

---

根据您的更新，这可能是您想要的：

module immShifter( input [31:0] in, input [3:0] rotate_imm, output [31:0] out );
  integer i, times_rotated;
  always @*
  begin
    times_rotated = rotate_imm << 1;
    for (i = 0; i < times_rotated; i++)
      $display("Hello, World");
    $display(""); // empty line as separate between changes to rotate_imm
  end
  assign out = in;
endmodule