【发布时间】：2015-03-11 08:19:34
【问题描述】：
我正在尝试做一个简单的寄存器。输入总线带来 256 位，而寄存器只需在其所有 8 个输出上记录 32 位。我不明白为什么它不起作用。它应该有一个同步加载和清除和一个异步加载和清除。
我在测试台上对其进行了测试。它不会更改输出上的任何值。我分别使用所有控制信号 aload、sload、aclr 和 sclr 进行了测试。什么都没有。。
VHDL模块代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VecReg is
port (
clk, sload, aload, sclr, aclr : in STD_LOGIC;
D : in std_logic_vector(255 downto 0);
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 : out std_logic_vector(31 downto 0)
);
end entity VecReg;
architecture VecRegArch of VecReg is
begin
a1 : process(aload,aclr)
begin
if(aload = '1') then
Q0 <= D(31 downto 0);
Q1 <= D(63 downto 32);
Q2 <= D(95 downto 64);
Q3 <= D(127 downto 96);
Q4 <= D(159 downto 128);
Q5 <= D(191 downto 160);
Q6 <= D(223 downto 192);
Q7 <= D(255 downto 224);
elsif(aclr = '1') then
Q0 <= x"00000000";
Q1 <= x"00000000";
Q2 <= x"00000000";
Q3 <= x"00000000";
Q4 <= x"00000000";
Q5 <= x"00000000";
Q6 <= x"00000000";
Q7 <= x"00000000";
end if;
end process a1;
main : process(clk)
begin
if (rising_edge(clk)) and (sload = '1') then
Q7 <= D(255 downto 224);
Q6 <= D(223 downto 192);
Q5 <= D(191 downto 160);
Q4 <= D(159 downto 128);
Q3 <= D(127 downto 96);
Q2 <= D(95 downto 64);
Q1 <= D(63 downto 32);
Q0 <= D(31 downto 0);
end if;
if (rising_edge(clk)) and (sclr = '1') then
Q0 <= x"00000000";
Q1 <= x"00000000";
Q2 <= x"00000000";
Q3 <= x"00000000";
Q4 <= x"00000000";
Q5 <= x"00000000";
Q6 <= x"00000000";
Q7 <= x"00000000";
end if;
end process main;
end architecture VecRegArch;
VHDL 测试平台代码：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY imame IS
END imame;
ARCHITECTURE behavior OF imame IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VecReg
PORT(
clk : IN std_logic;
sload : IN std_logic;
aload : IN std_logic;
sclr : IN std_logic;
aclr : IN std_logic;
D : IN std_logic_vector(255 downto 0);
Q0 : OUT std_logic_vector(31 downto 0);
Q1 : OUT std_logic_vector(31 downto 0);
Q2 : OUT std_logic_vector(31 downto 0);
Q3 : OUT std_logic_vector(31 downto 0);
Q4 : OUT std_logic_vector(31 downto 0);
Q5 : OUT std_logic_vector(31 downto 0);
Q6 : OUT std_logic_vector(31 downto 0);
Q7 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal sload : std_logic := '0';
signal aload : std_logic := '0';
signal sclr : std_logic := '0';
signal aclr : std_logic := '0';
signal D : std_logic_vector(255 downto 0) := (others => '0');
--Outputs
signal Q0 : std_logic_vector(31 downto 0);
signal Q1 : std_logic_vector(31 downto 0);
signal Q2 : std_logic_vector(31 downto 0);
signal Q3 : std_logic_vector(31 downto 0);
signal Q4 : std_logic_vector(31 downto 0);
signal Q5 : std_logic_vector(31 downto 0);
signal Q6 : std_logic_vector(31 downto 0);
signal Q7 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 100 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VecReg PORT MAP (
clk => clk,
sload => sload,
aload => aload,
sclr => sclr,
aclr => aclr,
D => D,
Q0 => Q0,
Q1 => Q1,
Q2 => Q2,
Q3 => Q3,
Q4 => Q4,
Q5 => Q5,
Q6 => Q6,
Q7 => Q7
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
aload <= '0';
sload <= '0';
aclr <= '0';
sclr <= '0';
wait for 500 us;
D <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
wait for 40 us;
aload <= '1';
wait for 1000 us;
aload <= '0';
--wait for 60 ns;
--sload <= '0';
--aload <= '0';
--aclr <= '1';
--wait for 200 ns;
--sclr <= '1';
--wait for 300 ns;
--D <= x"1010111010101110101011101010111010101110101011101010111010101110";
--aload <= '1';
--wait for 400 ns;
--aclr <= '1';
end process;
END;
【问题讨论】：
-
详细模型中的每个流程都有自己的驱动程序。如果已解析数据类型信号（例如 std_logic_vector）有多个驱动程序，则该信号的值将由解析函数确定。 （在这种情况下，解析函数位于包 std_logic_1164 中）。并且除了子程序之外的所有内容都在详细说明时演变为 VHDL 中的块语句和等效过程。两个进程，两个驱动，值就是解析出来的值。