VHDL 在 RAM 中设置常量数据

Question

最近我正在使用 VHDL 编写一个 16-but RAM。我的代码是：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.Numeric_Std.all;

entity RAM is
port(
PC_in: in std_logic_vector (5 downto 0);
EN_WR_in: in std_logic_vector (1 downto 0);
RAM_in : in std_logic_vector(15 downto 0);
RAM_out : out std_logic_vector(15 downto 0);
test : out integer
);


end RAM;

architecture Behavioral of RAM is
type ram_t is array (63 downto 0) of std_logic_vector(15 downto 0);
signal ram : ram_t;
begin
PROCESS (EN_WR_in)
BEGIN
        if (EN_WR_in(1)='1') then

        IF (EN_WR_in(0) = '1') THEN
            ram(conv_integer(unsigned(PC_in))) <= RAM_in;
             else
        RAM_out <= ram(conv_integer(unsigned(PC_in)));
        end if;

        else

        RAM_out <="ZZZZZZZZZZZZZZZZ";

        end if;

END PROCESS;
     ram(20) <= "0000100010010000";
end Behavioral;

我面临的问题是我需要在 ram 中设置一些常量数据，就像

ram(20) <= "0000100010010000";

但在模拟过程中不存在常量数据。有什么办法解决吗？

谢谢。

Answer 1

你可以在声明时初始化ram：

signal ram : ram_t := ( "0000100010010000", x"1234", ... );

或许

signal ram : ram_t := ( 20 => "0000100010010000", others => (others=>'0') );